This invention relates to a semiconductor integrated circuit device having an SOI (Silicon on Insulator) structure. More particularly, the invention is concerned with an SOI static electricity protection circuit for preventing an internal circuit from being damaged due to static electricity or the like to be inputted through the input/output pad, and the internal circuit.
In general, a static electricity protection circuit is provided between an input/output pad and an internal circuit to instantaneously release high voltage, such as static electricity, having been inputted through the input/output pad into regions other than the internal circuit (silicon substrate or the like). Due to this, the internal circuit (particularly, a MOSFET gate oxide film) is prevented from being damaged due to a high voltage as this.
The static electricity protection circuits as above involve avalanche breakdown at PN junctions, snap back owing to MOSFET bipolar operation, punch through by punch-through devices, and so on. The static electricity protection circuits of these types have a performance that the possibility of applying a high voltage to an internal circuit can be decreased with decrease in resistance over a high-voltage releasing path. Furthermore, prevention is also made against thermal breakdown to be caused due to flow of an overcurrent by the static electricity protection circuit itself. That is, static electricity protection performance is enhanced. The resistance is almost determined principally by an area of a PN junction of the static electricity protection circuit through which a high voltage current is to flow and a volume of a substrate.
For static electricity protection circuits made in a bulk structure, the PN junction has an area corresponding to an area of a side surface plus that of a bottom surface thereof, accordingly being sufficient in junction area. Also, the volume is sufficient because the substrate itself corresponds to a bulk.
Meanwhile, the SOI structure includes a buried oxide film on a silicon substrate, and a silicon layer of a first conductivity type in which semiconductor elements are to be built on the buried oxide film.
Recently, in order to realize high speed operation with low power consumption for an internal circuit formed in a silicon layer, there are necessities to completely deplete a MOSFET forming an internal circuit and reduce source and drain capacitance. Due to this, there is a tendency of decreasing the thickness of a silicon layer. In a case that a static electricity protection circuit made in a bulk structure for a semiconductor device is applied directly to a semiconductor device having an SOI structure as stated before, the reduction in silicon layer thickness is meant to decrease the volume of a substrate due to a reduction in thickness of the first conductivity type silicon layer as a substrate besides the decrease in PN junction area due to reduction in PN junction side surface area and losing a bottom surface area.
That is, recently there has been a difficulty in applying a static electricity protection circuit made in a bulk structure for a semiconductor device directly to an SOI-structured semiconductor device, because of the reason as discussed above.